1. Field of the Invention
The present invention relates to a process for fabricating a chip package structure. More particularly, the present invention relates to a process for fabricating a chip embedded package structure.
2. Description of Related Art
In this electronic age, multi-functional, highly integrated, miniaturized, inexpensive devices with a high processing speed are in great demand. To meet this trend, chip packages are also highly miniaturized and densified. In the conventional ball grid array (BGA) packaging technique, a package substrate is often used as a carrier for an integrated circuit (IC) chip. The chip disposed over the package substrate is electrically connected to the substrate through flip chip bonding or wire bonding. An array of solder balls is also attached to the bottom surface of the package substrate. Hence, the chip is able to electrically connect with the electronic devices in another level such as a printed circuit board through an inner circuit within the package substrate and the solder balls at the bottom of the package substrate.
However, the BGA packaging technique needs to deploy a package substrate with a high layout density and electrically connect using either the flip chip or wire bonding technique. Hence, the signal transmission pathway is slightly longer. To reduce the transmission pathway, a chip embedded package structure having a bump-less build-up layer (BBUL) has been developed. In the chip embedded package, the step of connecting a chip to a package substrate through flip-chip or wire bonding is unnecessary. This is because a multi-layered interconnection structure is directly formed on the active surface of the chip and an array of contacts such as solder balls or pins for connecting with higher level electronic devices is directly formed on the multi-layered interconnection structure thereafter.
FIGS. 1A through 1F are schematic cross-sectional views showing the steps for forming a conventional chip package. First, as shown in FIG. 1A, a tape 110 and a stiffener 120 are provided. The stiffener 120 is attached to the tape 110 for increasing the structural strength and heat dissipating capability of the subsequently formed package. The stiffener 120 has a chip opening 122 for accommodating a chip 130 (shown in FIG. 1B) and the tape 110 covers the bottom end of the chip opening 122.
As shown in FIGS. 1B and 1C, a chip 130 having a plurality of bonding pads 134 on an active surface 132 is attached to the tape 110 within the chip opening 122. Thereafter, an encapsulating compound 140 is deposited to fill the chip opening 122 between the chip 130 and the stiffener 120. The tape 110 serves as a means of positioning and supporting the chip 130 inside the chip opening 122 before the chip 130 is properly fixed by the encapsulating compound 140. After fixing the position of the chip 130, the tape 110 is torn away and cleaned to ensure no residual tape remains.
As shown in FIG. 1D, a build-up process is performed to produce a multi-layered interconnection structure 150 on the active surface 132 of the chip 130 and the surface of the stiffener 120. The multi-layered interconnection structure 150 comprises a plurality of patterned circuit layers 152, at least a dielectric layer 154 and a plurality of conductive blind vias 156. The circuit layers 152 are sequentially stacked over the active surface 132 of the chip 130 and the surface of the stiffener 120 and connected to the bonding pads 134 of the chip 130. Each dielectric layer 154 is disposed between two neighboring circuit layers 152. Furthermore, the conductive blind vias 156 pass through one of the dielectric layer 154 and at least electrically connect two circuit layers 152 together. The circuit layers 152 and the conductive blind vias 156 together form an inner circuit 158. The inner circuit 158 also has a plurality of metallic pads 159 exposed on the outer surface of the multi-layered interconnection structure 150.
As shown in FIG. 1E, a solder mask layer 160 is formed over the multi-layered interconnection structure 150. The solder mask layer 160 has a plurality of openings 162 that exposes the metallic pads 159 respectively.
As shown in FIG. 1F, a layer of pre-soldering material is printed over the openings 162 of the solder mask layer 160. Thereafter, a plurality of conductive pins 180 is bonded to the pre-soldering material 170 to form a complete chip package structure 100.
The aforementioned process of forming the package has the following drawbacks. The tape needs to be torn away and the surface needs to be cleaned so that the process is complicated but trivial. Moreover, after tearing the tape away from the chip and the stiffener, coplanarity between the chip and the stiffener is hard to maintain. Ultimately, this may reduce the reliability of the subsequently formed multi-layered interconnection structure. In addition, no alignment marks are set up for performing laser drilling or photolithographic process during the fabrication of the multi-layered interconnection structure. Without any alignment mark to enhance processing accuracy, it is difficult to increase the overall yield of the packaging.